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utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? features access time : 55/70/100 ns cmos low operating power operating : 45/35/25ma (max.) standby : 20a (typ.) l-version 3a (typ.) ll-version single 2.7v~3.6v power supply industrial temperature : -40 ~85 all inputs and outputs ttl compatible fully static operation three state outputs data retention voltage : 1.5v (min) package : 32-pin 450 mil sop 32-pin 8mm20mm tsop-i 32-pin 8mm13.4mm stsop 36-pin 6mm8mm tfbga general description the ut62l5128 is a 4,194,304-bit low power cmos static random ac cess memory organized as 524,288 words by 8 bits. it is fabricated using high performance, high reliability cmos technology. the ut62l5128 operates from a wide range 2.7v~3.6v power supply and all inputs and outputs are fully ttl compatible. the ut62l5128 supports industrial operating temperature range, and supports low data retention voltage for battery back-up operation with low data retention current. functional block diagram decoder i/o data circuit control circuit 512k 8 memory array column i/o oe we a0-a18 vcc vss i/o1-i/o8 ce
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? pin configuration sop a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 a17 a8 a9 a11 a10 i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 vss 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 a13 a14 a18 a16 vcc a15 29 30 31 32 oe ce we i/o4 a11 a9 a8 a13 i/o3 a10 a14 a12 a7 a6 a5 vcc i/o8 i/o7 i/o6 i/o5 vss i/o2 i/o1 a0 a1 a2 a4 a3 tsop-1 / stsop 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 we oe ce a17 a18 a15 32 31 30 29 a16 oe ce we a12 a11 a13 nc a17 a10 a14 a15 i/o6 i/o7 i/o8 a9 vss a8 a16 i/o5 vcc vcc i/o4 a18 vss a7 a0 i/o3 i/o2 i/o1 a6 a1 a3 a5 nc a4 a2 123456 h g c d e f a b tfbga pin description symbol description a0 - a18 address inputs i/o1 - i/o8 data inputs/outputs ce chip enable input we write enable input oe output enable input vcc power supply vss ground nc no connection
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? absolute maximum ratings * parameter symbol rating unit terminal voltage with respect to v ss v term -0.5 to 4.6 v operating temperature industrial t a -40 to 85 storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 secs) tsolder 260 *stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the dev ice or any other conditions above those i ndicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity. truth table mode we ce oe i/o operation supply current standby x h x high ? z i sb , i sb1 output disable h l h high ? z i cc , i cc1, i cc2 read h l l d out i cc , i cc1, i cc2 write l l x d in i cc , i cc1, i cc2 note: h = v ih , l=v il , x = don't care. dc electrical characteristics (v cc = 2.7v~3.6v, t a = -40 to 85 ) parameter symbol test condition min. typ. max. unit power voltage v cc 2.7 3.0 3.6 v input high voltage v ih 2.0 - v cc +0.3 v input low voltage v il -0.2 - 0.6 v input leakage current i li v ss Q v in Q v cc - 1 - 1 a output leakage current i lo v ss Q v i/o Q v cc; output disabled - 1 - 1 a output high voltage v oh i oh = -1ma 2.2 - - v output low voltage v ol i ol = 2.1ma - - 0.4 v 55 - 30 45 ma 70 - 25 35 ma operating power supply current i cc cycle time=min, 100%duty, i i/o =0ma, ce =v il ; 100 - 20 25 ma i cc1 cycle time=1 s,100%duty,i i/o =0ma, ce Q 0.2v,other pins at 0.2v or vcc-0.2v, - 4 5 ma average operation current i cc2 cycle time=500ns,100%duty,i i/o =0ma, ce Q 0.2v,other pins at 0.2v or vcc-0.2v, - 8 10 ma standby current (ttl) i sb ce =v ih, other pins = v ih or v il ; - 0.3 0.5 ma -l - 20 80 a standby current (cmos) i sb1 ce =v cc -0.2v, other pins at 0.2v or vcc-0.2v, -ll - 3 25 a
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? capacitance (t a =25 , f=1.0mhz) parameter symbol min. max unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0v to 3.0v input rise and fall times 5ns input and output timing reference levels 1.5v output load c l = 30pf+1ttl , i oh /i ol = -1ma / 2.1ma ac electrical characteristics (v cc = 2.7v~3.6v , t a = -40 to 85 ) (1) read cycle ut62l5128-55 ut62l5128-70 ut62l5128-100 parameter symbol min. max. min. max. min. max. unit read cycle time t rc 55 - 70 - 100 - ns address access time t aa - 55 - 70 - 100 ns chip enable access time t ace - 55 - 70 - 100 ns output enable access time t oe - 30 - 35 - 50 ns chip enable to output in low z t clz* 10 - 10 - 10 - ns output enable to output in low z t olz* 5 - 5 - 5 - ns chip disable to output in high z t chz* - 20 - 25 - 30 ns output disable to output in high z t ohz* - 20 - 25 - 30 ns output hold from address change t oh 10 - 10 - 10 - ns (2) write cycle ut62l5128-55 ut62l5128-70 ut62l5128-100 parameter symbol min. max. min. max. min. max. unit write cycle time t wc 55 - 70 - 100 - ns address valid to end of write t aw 50 - 60 - 80 - ns chip enable to end of write t cw 50 - 60 - 80 - ns address set-up time t as 0 - 0 - 0 - ns write pulse width t wp 45 - 55 - 70 - ns write recovery time t wr 0 - 0 - 0 - ns data to write time overlap t dw 25 - 30 - 40 - ns data hold from end of write time t dh 0 - 0 - 0 - ns output active from end of write t ow* 5 - 5 - 5 - ns write to output in high z t whz* - 30 - 30 - 40 ns *these parameters are guaranteed by device char acterization, but not production tested.
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? timing waveforms read cycle 1 (address controlled) (1,2,4) t rc address dout data valid t aa t oh t oh read cycle 2 ( ce and oe controlled) (1,3,5,6) t rc t aa t ace t oe t chz t ohz t clz t oh t olz high-z data valid high-z address ce oe dout notes : 1. we is high for read cycle. 2. device is continuously selected ce =v il. 3. address must be valid prior to or coincident with ce transition; otherwise t aa is the limiting parameter. 4. oe is low. 5. t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 6. at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz.
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? write cycle 1 ( we controlled) (1,2,3,5) t wc t aw t cw t as t wp t whz t ow t dw t dh t wr address ce we dout din data valid high-z (4) (4) write cycle 2 ( ce controlled) (1,2,5) t wc t aw t cw t as t wr t wp t whz t dw t dh data valid address ce we dout din high-z notes : 1. we or ce must be high during all address transitions. 2. a write occurs during the overlap of a low ce and a low we . 3. during a we controlled with write cycle with oe low, t wp must be greater than t whz +t dw to allow the drivers to turn off and data to be placed on the bus. 4. during this period, i/o pins are in the output state, and input singals must not be applied. 5. if the ce low transition occurs simultaneously with or after we low transition, the outputs remain in a high impedance state. 6. t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state.
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? data retention characteristics (t a = -40 to 85 ) parameter symbol test condition min. typ. max. unit vcc for data retention v dr ce R v cc -0.2v 1.5 - 3.6 v vcc=1.5v - l - 1 50 a data retention current i dr ce R v cc -0.2v - ll - 0.5 20 a chip disable to data t cdr see data retention retention time waveforms (below) 0 - - ms recovery time t r 5 - - ms data retention waveform ( ce controlled) data retention mode v dr R 1.5v ce R v cc -0.2v v cc v cc v ih v ih v cc ce t r t cdr
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? package outline dimension 32 pin 450 mil sop package outline dimension unit symbol inch(ref) mm(base) a 0.118 (max) 2.997 (max) a1 0.004(min) 0.102(min) a2 0.111(max) 2.82(max) b 0.016(typ) 0.406(typ) c 0.008(typ) 0.203(typ) d 0.817(max) 20.75(max) e 0.445 0.005 11.303 0.127 e1 0.555 0.012 14.097 0.305 e 0.050(typ) 1.270(typ) l 0.0347 0.008 0.881 0.203 l1 0.055 0.008 1.397 0.203 s 0.026(max) 0.660 (max) y 0.004(max) 0.101(max) 0 o -10 o 0 o -10 o
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? 32 pin stsop package outline dimension 1 16 17 32 c l hd d "a" e e 12 (2x) 12 (2x) seating plane y 32 17 16 1 c a2 a1 l a 0.254 0 gauge plane 12 (2x) 12 (2x) seating plane "a" datail view l1 b unit symbol inch(base) mm(ref) a 0.049 (max) 1.25 (max) a1 0.005 0.002 0.130 0.05 a2 0.039 0.002 1.00 0.05 b 0.008 0.001 0.200 0.025 c 0.005 (typ) 0.127 (typ) d 0.465 0.004 11.800 0.100 e 0.315 0.004 8.000 0.100 e 0.020 (typ) 0.50 (typ) hd 0.528 0.008 13.40 0.20. l 0.0197 0.004 0.50 0.10 l1 0.0315 0.004 0.8 0.10 y 0.003 (max) 0.076 (max) 0 o ? 5 o 0 o ? 5 o
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? 32 pin tsop-i package outline dimension unit symbol inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.004 0.002 0.10 0.05 a2 0.039 0.002 1.00 0.05 b 0.008 + 0.002 - 0.001 0.20 + 0.05 -0.03 c 0.005 (typ) 0.127 (typ) d 0.724 0.004 18.40 0.10 e 0.315 0.004 8.00 0.10 e 0.020 (typ) 0.50 (typ) hd 0.787 0.008 20.00 0.20 l 0.0197 0.004 0.50 0.10 l1 0.0315 0.004 0.8 0.10 y 0.003 (max) 0.076 (max) 0 o ? 5 o 0 o ? 5 o
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 11 ? 36 pin tfbga package outline dimension a1 ball pad corner a b c d e f g h 1 2 3 4 5 6 a1 ball pad corner x y detail a bottom view ( ball side ) top view (die view ) 8.0 0.05 6.0 0.05 1.375 5.25 1.125 3.75 0.75 0.75 side view 0.55 0.32 0.02 0 0.23 0.03 1.2 max. z detail b 0.05 0.02 seating plane z detail a 0.1 z 0.08 z 0.1 z y x 0.05 z solder ball ?0.30(x36) 1.2 max.
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 12 ? ordering information part no. access time (ns) standby current (a) typ. package ut62l5128sc-55li 55 20 32 pin sop ut62l5128sc-55lli 55 3 32 pin sop ut62l5128sc-70li 70 20 32 pin sop ut62l5128sc-70lli 70 3 32 pin sop ut62l5128sc-100li 100 20 32 pin sop ut62l5128sc-100lli 100 3 32 pin sop ut62l5128ls-55li 55 20 32 pin stsop ut62l5128ls-55lli 55 3 32 pin stsop ut62l5128ls-70li 70 20 32 pin stsop ut62l5128ls-70lli 70 3 32 pin stsop ut62l5128ls-100li 100 20 32 pin stsop ut62l5128ls-100lli 100 3 32 pin stsop ut62l5128lc-55li 55 20 32 pin tsop- ut62l5128lc-55lli 55 3 32 pin tsop- ut62l5128lc-70li 70 20 32 pin tsop- ut62l5128lc-70lli 70 3 32 pin tsop- ut62l5128lc-100li 100 20 32 pin tsop- ut62l5128lc-100lli 100 3 32 pin tsop- ut62l5128bs-55li 55 20 36 pin tfbga ut62l5128bs-55lli 55 3 36 pin tfbga UT62L5128BS-70LI 70 20 36 pin tfbga ut62l5128bs-70lli 70 3 36 pin tfbga ut62l5128bs-100li 100 20 36 pin tfbga ut62l5128bs-100lli 100 3 36 pin tfbga
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 13 ? revision history revision description date preliminary rev. 0.5 original. mar, 2001 preliminary rev. 0.6 1. the symbols ce# and oe# and we# are revised as. ce and oe and we . 2. separate industrial and consumer spec. 3. add access time 55ns range. jun 21,2001 preliminary rev. 0.7 1. add sop and stsop package dec 18,2001
utron ut62l5128(i) preliminary rev. 0.7 512k x 8 bit low power cmos sram utron technology inc. p80052 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 14 ? this page is left blank intentionally.

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